LINK_TYPE_DSA_GSW1XX: add EDSA protocol for GSW1xx family. #51
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,104 @@ | ||
| <!-- Start of LINKTYPE_DSA_TAG_GSW1XX section --> | ||
| <div class="post"> | ||
| <h2 class="title"> | ||
| LINKTYPE_DSA_TAG_GSW1XX | ||
| </h2> | ||
| <div class="entry"> | ||
| <h3 class="subtitle">Packet structure</h3> | ||
| <ul> | ||
| The protocol is used by GSW120, GSW140, GSW141, GSW145 chips | ||
| and has a history with products from Infineon, Intel and MaxLinear. | ||
| The protocol information is based on the MaxLinear Data Sheet Revision 1.4. | ||
| </ul> | ||
| <h4 class="subtitle">Switch tag structure</h4> | ||
| <ul> | ||
| The gsw1xx special tagged frames contain a proprietary tag inserted | ||
| between the source address field and the EtherType/length field in the | ||
| Ethernet header. The Special Tag is 8 octets. It contains a | ||
| programmable EtherType value and a standard DSA tag. | ||
| Ingress and Egress have different formats. If byte 6&7 is not | ||
| zero it is a egress packet. | ||
| </ul> | ||
| Format of (Ethertyped) Ingress tagged frames: | ||
| <pre> | ||
| +0 +----+----+----+----+----+----+----+----+ | ||
|
Member
There was a problem hiding this comment. Please note indentation is off in the packet diagrams. |
||
| | Destination Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ | ||
| | Source Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ +- | ||
| | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| | Prog. DSA Ether Type [7:0] | | + | ||
|
Member
There was a problem hiding this comment. Special Tag Content ends in the middle of programmable EtherType in this packet diagram, should be exactly 6 bytes after EtherType according to the data sheet. |
||
| +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| |PME[7] TCE[6] TSE[5] FNL[4] TTC[3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | TEPML [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | TEPMH [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res[7:5] IE[4] SP[3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res [7:0] all zero | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res [7:0] all zero | | | | ||
| +1 +----+----+----+----+----+----+----+----+ +- +- | ||
| </pre> | ||
| Format of (Ethertyped) Egress tagged frames: | ||
| <pre> | ||
| +0 +----+----+----+----+----+----+----+----+ | ||
| | Destination Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ | ||
| | Source Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ +- | ||
| | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| | Prog. DSA Ether Type [7:0] | | + | ||
| +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| | TC[7:4] IPN [3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | PPPOE[7] IPV[6] IPO[5:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | DLPML [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | DLPMR [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | MI[7] KL2UM[6] PLHB[5:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | PLLB [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ +- +- | ||
| </pre> | ||
| <div> | ||
| <h4 class="subtitle">Bit field abbreviations</h4> | ||
| <ul> | ||
| <li>PME: Port map enable </li> | ||
| <li>IPN: Ingress port number</li> | ||
| <li>TCE: Traffic class enable</li> | ||
| <li>TSE: Time stamp enable</li> | ||
| <li>FNL: Force no learning</li> | ||
| <li>TC: Traffic class</li> | ||
| <li>IPV: IPv4 packet</li> | ||
| <li>IPO: IP offset</li> | ||
| <li>SP: Source port</li> | ||
| <li>IE: Interrupt enable</li> | ||
| <li>PPPOE: ppp-over-ethernet</li> | ||
| <li>DLPML: Destination logical port map low bits.</li> | ||
| <li>DLPMR: Destination logical port map high (reserved)</li> | ||
| <li>MI: Mirror indication</li> | ||
| <li>KL2UM Known l2 unicast/multicast mac.</li> | ||
| <li>PLHB: Packet Length High Bits</li> | ||
| <li>PLLB: Packet Length Low Bits</li> | ||
| <li>TEPML: Target egress port maps low bits</li> | ||
| <li>TEPMH: Target egress port maps high bits (reserved)</li> | ||
| <li>Res: Reserved</li> | ||
| </ul> | ||
| </div> | ||
| <h5 class="notes">Notes</h5> | ||
| Port mapping is a switch internal function for multi-cast and vlan | ||
| routing and need custom firmware rules to be active. | ||
| <br> | ||
| Precise Time Stamping indication according to IEEE 1588v2. | ||
| <br> | ||
| Special tag default value is 0x88C3 but can be changed with firmware. | ||
| </div> | ||
| </div> | ||
| <!-- End of LINKTYPE_DSA_TAG_GSW1XX section --> | ||
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| <!-- Start of LINKTYPE_DSA_TAG_GSW1XX section --> | ||
| <div class="post"> | ||
| <h2 class="title"> | ||
| LINKTYPE_DSA_TAG_GSW1XX | ||
| </h2> | ||
| <div class="entry"> | ||
| <h3 class="subtitle">Packet structure</h3> | ||
| <ul> | ||
| The protocol is used by GSW120, GSW140, GSW141, GSW145 chips | ||
| and has a history with products from Infineon, Intel and MaxLinear. | ||
| The protocol information is based on the MaxLinear Data Sheet Revision 1.4. | ||
| </ul> | ||
| <h4 class="subtitle">Switch tag structure</h4> | ||
| <ul> | ||
| The gsw1xx special tagged frames contain a proprietary tag inserted | ||
| between the source address field and the EtherType/length field in the | ||
| Ethernet header. The Special Tag is 8 octets. It contains a | ||
| programmable EtherType value and a standard DSA tag. | ||
| Ingress and Egress have different formats. If byte 6&7 is not | ||
| zero it is a egress packet. | ||
| </ul> | ||
| Format of (Ethertyped) Ingress tagged frames: | ||
| <pre> | ||
| +0 +----+----+----+----+----+----+----+----+ | ||
| | Destination Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ | ||
| | Source Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ +- | ||
| | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| | Prog. DSA Ether Type [7:0] | | + | ||
| +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| |PME[7] TCE[6] TSE[5] FNL[4] TTC[3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | TEPML [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | TEPMH [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res[7:5] IE[4] SP[3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res [7:0] all zero | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | Res [7:0] all zero | | | | ||
| +1 +----+----+----+----+----+----+----+----+ +- +- | ||
| </pre> | ||
| Format of (Ethertyped) Egress tagged frames: | ||
| <pre> | ||
| +0 +----+----+----+----+----+----+----+----+ | ||
| | Destination Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ | ||
| | Source Address (6 octets) | | ||
| +6 +----+----+----+----+----+----+----+----+ +- | ||
| | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| | Prog. DSA Ether Type [7:0] | | + | ||
| +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| | TC[7:4] IPN [3:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | PPPOE[7] IPV[6] IPO[5:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | DLPML [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | DLPMR [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | MI[7] KL2UM[6] PLHB[5:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ | | | ||
| | PLLB [7:0] | | | | ||
| +1 +----+----+----+----+----+----+----+----+ +- +- | ||
| </pre> | ||
| <div> | ||
| <h4 class="subtitle">Bit field abbreviations</h4> | ||
| <ul> | ||
| <li>PME: Port map enable </li> | ||
| <li>IPN: Ingress port number</li> | ||
| <li>TCE: Traffic class enable</li> | ||
| <li>TSE: Time stamp enable</li> | ||
| <li>FNL: Force no learning</li> | ||
| <li>TC: Traffic class</li> | ||
| <li>IPV: IPv4 packet</li> | ||
| <li>IPO: IP offset</li> | ||
| <li>SP: Source port</li> | ||
| <li>IE: Interrupt enable</li> | ||
| <li>PPPOE: ppp-over-ethernet</li> | ||
| <li>DLPML: Destination logical port map low bits.</li> | ||
| <li>DLPMR: Destination logical port map high (reserved)</li> | ||
| <li>MI: Mirror indication</li> | ||
| <li>KL2UM Known l2 unicast/multicast mac.</li> | ||
| <li>PLHB: Packet Length High Bits</li> | ||
| <li>PLLB: Packet Length Low Bits</li> | ||
| <li>TEPML: Target egress port maps low bits</li> | ||
| <li>TEPMH: Target egress port maps high bits (reserved)</li> | ||
| <li>Res: Reserved</li> | ||
| </ul> | ||
| </div> | ||
| <h5 class="notes">Notes</h5> | ||
| Port mapping is a switch internal function for multi-cast and vlan | ||
| routing and need custom firmware rules to be active. | ||
| <br> | ||
| Precise Time Stamping indication according to IEEE 1588v2. | ||
| <br> | ||
| Special tag default value is 0x88C3 but can be changed with firmware. | ||
| </div> | ||
| </div> | ||
| <!-- End of LINKTYPE_DSA_TAG_GSW1XX section --> | ||
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| <!-- END OF PAGE CONTENTS --> | ||
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This should be 303 and should appear after
LINKTYPE_EDK2_MMbelow because the table is sorted by numeric ID.There was a problem hiding this comment.
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Correction: it should be 304, let me add the latest assignment to the table first.
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Done. Please use the latest master branch and make it 304.