Skip to content

Commit e649af3

Browse files
hathachhathach
committed
add lpc55s28 sdk 2.8.2
1 parent f7314b3 commit e649af3

File tree

122 files changed

+172220
-0
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

122 files changed

+172220
-0
lines changed

‎sdk/devices/LPC55S28/LPC55S28.h‎

Lines changed: 26900 additions & 0 deletions
Large diffs are not rendered by default.

‎sdk/devices/LPC55S28/LPC55S28.xml‎

Lines changed: 82529 additions & 0 deletions
Large diffs are not rendered by default.

‎sdk/devices/LPC55S28/LPC55S28_features.h‎

Lines changed: 375 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,375 @@
1+
/*
2+
** ###################################################################
3+
** Version: rev. 1.1, 2019-05-16
4+
** Build: b200401
5+
**
6+
** Abstract:
7+
** Chip specific module features.
8+
**
9+
** Copyright 2016 Freescale Semiconductor, Inc.
10+
** Copyright 2016-2020 NXP
11+
** All rights reserved.
12+
**
13+
** SPDX-License-Identifier: BSD-3-Clause
14+
**
15+
** http: www.nxp.com
16+
** mail: support@nxp.com
17+
**
18+
** Revisions:
19+
** - rev. 1.0 (2018-08-22)
20+
** Initial version based on v0.2UM
21+
** - rev. 1.1 (2019-05-16)
22+
** Initial A1 version based on v1.3UM
23+
**
24+
** ###################################################################
25+
*/
26+
27+
#ifndef _LPC55S28_FEATURES_H_
28+
#define _LPC55S28_FEATURES_H_
29+
30+
/* SOC module features */
31+
32+
/* @brief CASPER availability on the SoC. */
33+
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
34+
/* @brief CRC availability on the SoC. */
35+
#define FSL_FEATURE_SOC_CRC_COUNT (1)
36+
/* @brief CTIMER availability on the SoC. */
37+
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
38+
/* @brief DMA availability on the SoC. */
39+
#define FSL_FEATURE_SOC_DMA_COUNT (2)
40+
/* @brief FLASH availability on the SoC. */
41+
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
42+
/* @brief FLEXCOMM availability on the SoC. */
43+
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
44+
/* @brief GINT availability on the SoC. */
45+
#define FSL_FEATURE_SOC_GINT_COUNT (2)
46+
/* @brief GPIO availability on the SoC. */
47+
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
48+
/* @brief SECGPIO availability on the SoC. */
49+
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
50+
/* @brief HASHCRYPT availability on the SoC. */
51+
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
52+
/* @brief I2C availability on the SoC. */
53+
#define FSL_FEATURE_SOC_I2C_COUNT (8)
54+
/* @brief I2S availability on the SoC. */
55+
#define FSL_FEATURE_SOC_I2S_COUNT (8)
56+
/* @brief INPUTMUX availability on the SoC. */
57+
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
58+
/* @brief IOCON availability on the SoC. */
59+
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
60+
/* @brief LPADC availability on the SoC. */
61+
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
62+
/* @brief MRT availability on the SoC. */
63+
#define FSL_FEATURE_SOC_MRT_COUNT (1)
64+
/* @brief OSTIMER availability on the SoC. */
65+
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
66+
/* @brief PINT availability on the SoC. */
67+
#define FSL_FEATURE_SOC_PINT_COUNT (1)
68+
/* @brief SECPINT availability on the SoC. */
69+
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
70+
/* @brief PMC availability on the SoC. */
71+
#define FSL_FEATURE_SOC_PMC_COUNT (1)
72+
/* @brief PUF availability on the SoC. */
73+
#define FSL_FEATURE_SOC_PUF_COUNT (1)
74+
/* @brief LPC_RNG1 availability on the SoC. */
75+
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
76+
/* @brief RTC availability on the SoC. */
77+
#define FSL_FEATURE_SOC_RTC_COUNT (1)
78+
/* @brief SCT availability on the SoC. */
79+
#define FSL_FEATURE_SOC_SCT_COUNT (1)
80+
/* @brief SDIF availability on the SoC. */
81+
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
82+
/* @brief SPI availability on the SoC. */
83+
#define FSL_FEATURE_SOC_SPI_COUNT (9)
84+
/* @brief SYSCON availability on the SoC. */
85+
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
86+
/* @brief SYSCTL1 availability on the SoC. */
87+
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
88+
/* @brief USART availability on the SoC. */
89+
#define FSL_FEATURE_SOC_USART_COUNT (8)
90+
/* @brief USB availability on the SoC. */
91+
#define FSL_FEATURE_SOC_USB_COUNT (1)
92+
/* @brief USBFSH availability on the SoC. */
93+
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
94+
/* @brief USBHSD availability on the SoC. */
95+
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
96+
/* @brief USBHSH availability on the SoC. */
97+
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
98+
/* @brief USBPHY availability on the SoC. */
99+
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
100+
/* @brief UTICK availability on the SoC. */
101+
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
102+
/* @brief WWDT availability on the SoC. */
103+
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
104+
105+
/* LPADC module features */
106+
107+
/* @brief FIFO availability on the SoC. */
108+
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
109+
/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
110+
#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
111+
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
112+
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
113+
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
114+
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
115+
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
116+
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
117+
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
118+
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
119+
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
120+
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
121+
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
122+
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
123+
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
124+
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
125+
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
126+
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
127+
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
128+
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
129+
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
130+
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
131+
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
132+
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
133+
/* @brief Has calibration (bitfield CFG[CALOFS]). */
134+
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
135+
/* @brief Has offset trim (register OFSTRIM). */
136+
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
137+
/* @brief Has internal temperature sensor. */
138+
#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
139+
/* @brief Temperature sensor parameter A (slope). */
140+
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
141+
/* @brief Temperature sensor parameter B (offset). */
142+
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
143+
/* @brief Temperature sensor parameter Alpha. */
144+
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
145+
/* @brief the buffer size of temperature sensor. */
146+
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
147+
148+
/* CASPER module features */
149+
150+
/* @brief Base address of the CASPER dedicated RAM */
151+
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
152+
/* @brief Interleaving of the CASPER dedicated RAM */
153+
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
154+
/* @brief CASPER dedicated RAM offset */
155+
#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
156+
157+
/* DMA module features */
158+
159+
/* @brief Number of channels */
160+
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
161+
/* @brief Align size of DMA descriptor */
162+
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
163+
/* @brief DMA head link descriptor table align size */
164+
#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
165+
166+
/* FLEXCOMM module features */
167+
168+
/* @brief FLEXCOMM0 USART INDEX 0 */
169+
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
170+
/* @brief FLEXCOMM0 SPI INDEX 0 */
171+
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
172+
/* @brief FLEXCOMM0 I2C INDEX 0 */
173+
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
174+
/* @brief FLEXCOMM0 I2S INDEX 0 */
175+
#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
176+
/* @brief FLEXCOMM1 USART INDEX 1 */
177+
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
178+
/* @brief FLEXCOMM1 SPI INDEX 1 */
179+
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
180+
/* @brief FLEXCOMM1 I2C INDEX 1 */
181+
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
182+
/* @brief FLEXCOMM1 I2S INDEX 1 */
183+
#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
184+
/* @brief FLEXCOMM2 USART INDEX 2 */
185+
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
186+
/* @brief FLEXCOMM2 SPI INDEX 2 */
187+
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
188+
/* @brief FLEXCOMM2 I2C INDEX 2 */
189+
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
190+
/* @brief FLEXCOMM2 I2S INDEX 2 */
191+
#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
192+
/* @brief FLEXCOMM3 USART INDEX 3 */
193+
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
194+
/* @brief FLEXCOMM3 SPI INDEX 3 */
195+
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
196+
/* @brief FLEXCOMM3 I2C INDEX 3 */
197+
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
198+
/* @brief FLEXCOMM3 I2S INDEX 3 */
199+
#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
200+
/* @brief FLEXCOMM4 USART INDEX 4 */
201+
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
202+
/* @brief FLEXCOMM4 SPI INDEX 4 */
203+
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
204+
/* @brief FLEXCOMM4 I2C INDEX 4 */
205+
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
206+
/* @brief FLEXCOMM4 I2S INDEX 4 */
207+
#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
208+
/* @brief FLEXCOMM5 USART INDEX 5 */
209+
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
210+
/* @brief FLEXCOMM5 SPI INDEX 5 */
211+
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
212+
/* @brief FLEXCOMM5 I2C INDEX 5 */
213+
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
214+
/* @brief FLEXCOMM5 I2S INDEX 5 */
215+
#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
216+
/* @brief FLEXCOMM6 USART INDEX 6 */
217+
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
218+
/* @brief FLEXCOMM6 SPI INDEX 6 */
219+
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
220+
/* @brief FLEXCOMM6 I2C INDEX 6 */
221+
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
222+
/* @brief FLEXCOMM6 I2S INDEX 6 */
223+
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
224+
/* @brief FLEXCOMM7 USART INDEX 7 */
225+
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
226+
/* @brief FLEXCOMM7 SPI INDEX 7 */
227+
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
228+
/* @brief FLEXCOMM7 I2C INDEX 7 */
229+
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
230+
/* @brief FLEXCOMM7 I2S INDEX 7 */
231+
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
232+
/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
233+
#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
234+
/* @brief I2S has DMIC interconnection */
235+
#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
236+
237+
/* HASHCRYPT module features */
238+
239+
/* @brief the address of alias offset */
240+
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
241+
242+
/* I2S module features */
243+
244+
/* @brief I2S support dual channel transfer. */
245+
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
246+
/* @brief I2S has DMIC interconnection. */
247+
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
248+
249+
/* IOCON module features */
250+
251+
/* @brief Func bit field width */
252+
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
253+
254+
/* MRT module features */
255+
256+
/* @brief number of channels. */
257+
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
258+
259+
/* PINT module features */
260+
261+
/* @brief Number of connected outputs */
262+
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
263+
264+
/* PLU module features */
265+
266+
/* @brief Has WAKEINT_CTRL register. */
267+
#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
268+
269+
/* POWERLIB module features */
270+
271+
/* @brief Powerlib API is different with other LPC series devices. */
272+
#define FSL_FEATURE_POWERLIB_EXTEND (1)
273+
274+
/* PUF module features */
275+
276+
/* @brief Number of PUF key slots available on device. */
277+
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
278+
/* @brief the shift status value */
279+
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
280+
281+
/* SCT module features */
282+
283+
/* @brief Number of events */
284+
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
285+
/* @brief Number of states */
286+
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
287+
/* @brief Number of match capture */
288+
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
289+
/* @brief Number of outputs */
290+
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
291+
292+
/* SDIF module features */
293+
294+
/* @brief FIFO depth, every location is a WORD */
295+
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
296+
/* @brief Max DMA buffer size */
297+
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
298+
/* @brief Max source clock in HZ */
299+
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
300+
/* @brief support 2 cards */
301+
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
302+
303+
/* SECPINT module features */
304+
305+
/* @brief Number of connected outputs */
306+
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
307+
308+
/* SYSCON module features */
309+
310+
/* @brief Flash page size in bytes */
311+
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
312+
/* @brief Flash sector size in bytes */
313+
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
314+
/* @brief Flash size in bytes */
315+
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
316+
/* @brief Has Power Down mode */
317+
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
318+
/* @brief CCM_ANALOG availability on the SoC. */
319+
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
320+
/* @brief Starter register discontinuous. */
321+
#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
322+
323+
/* USB module features */
324+
325+
/* @brief Size of the USB dedicated RAM */
326+
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
327+
/* @brief Base address of the USB dedicated RAM */
328+
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
329+
/* @brief USB version */
330+
#define FSL_FEATURE_USB_VERSION (200)
331+
/* @brief Number of the endpoint in USB FS */
332+
#define FSL_FEATURE_USB_EP_NUM (5)
333+
334+
/* USBFSH module features */
335+
336+
/* @brief Size of the USB dedicated RAM */
337+
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
338+
/* @brief Base address of the USB dedicated RAM */
339+
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
340+
/* @brief USBFSH version */
341+
#define FSL_FEATURE_USBFSH_VERSION (200)
342+
343+
/* USBHSD module features */
344+
345+
/* @brief Size of the USB dedicated RAM */
346+
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
347+
/* @brief Base address of the USB dedicated RAM */
348+
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
349+
/* @brief USBHSD version */
350+
#define FSL_FEATURE_USBHSD_VERSION (300)
351+
/* @brief Number of the endpoint in USB HS */
352+
#define FSL_FEATURE_USBHSD_EP_NUM (6)
353+
354+
/* USBHSH module features */
355+
356+
/* @brief Size of the USB dedicated RAM */
357+
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
358+
/* @brief Base address of the USB dedicated RAM */
359+
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
360+
/* @brief USBHSH version */
361+
#define FSL_FEATURE_USBHSH_VERSION (300)
362+
363+
/* UTICK module features */
364+
365+
/* @brief UTICK does not support PD configure. */
366+
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
367+
368+
/* WWDT module features */
369+
370+
/* @brief WWDT does not support oscillator lock. */
371+
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
372+
/* @brief WWDT does not support power down configure */
373+
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
374+
375+
#endif /* _LPC55S28_FEATURES_H_ */

‎sdk/devices/LPC55S28/arm/LPC55XX_512.FLM‎

21.8 KB
Binary file not shown.

‎sdk/devices/LPC55S28/arm/LPC55xx.dbgconf‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
// <<< Use Configuration Wizard in Context Menu >>>
2+
3+
// <o0> SWO pin
4+
// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
5+
// <i> for an external debug tool to evaluate.
6+
// <0=> PIO0_10
7+
// <1=> PIO0_8
8+
SWO_Pin = 0;
9+
//
10+
11+
// <h>Debug Configuration
12+
// <o.0> StopAfterBootloader <i> Stop after Bootloader
13+
// </h>
14+
Dbg_CR = 0x00000001;
15+
//
16+
17+
18+
// <<< end of configuration section >>>

0 commit comments

Comments
 (0)