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robert-hhrobert-hh
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nxp_driver: Update MIMXRT files to version 2.11.
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527 files changed

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‎sdk/devices/MIMXRT1011/MIMXRT1011.h‎

Lines changed: 6593 additions & 1438 deletions
Large diffs are not rendered by default.

‎sdk/devices/MIMXRT1011/MIMXRT1011.xml‎

Lines changed: 17132 additions & 15157 deletions
Large diffs are not rendered by default.

‎sdk/devices/MIMXRT1011/MIMXRT1011_features.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.0, 2019-08-01
4-
** Build: b210329
4+
** Build: b211108
55
**
66
** Abstract:
77
** Chip specific module features.
@@ -87,8 +87,6 @@
8787
#define FSL_FEATURE_SOC_PMU_COUNT (1)
8888
/* @brief PWM availability on the SoC. */
8989
#define FSL_FEATURE_SOC_PWM_COUNT (1)
90-
/* @brief ROMC availability on the SoC. */
91-
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
9290
/* @brief SNVS availability on the SoC. */
9391
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
9492
/* @brief SPDIF availability on the SoC. */
@@ -130,9 +128,9 @@
130128
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
131129
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
132130
/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
133-
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (0)
131+
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1)
134132
/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
135-
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (0)
133+
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1)
136134

137135
/* AOI module features */
138136

@@ -290,6 +288,8 @@
290288
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
291289
/* @brief Has separate DMA RX and TX requests. */
292290
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
291+
/* @brief Has CCR1 (related to existence of registers CCR1). */
292+
#define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
293293

294294
/* LPUART module features */
295295

@@ -379,7 +379,7 @@
379379
/* @brief OTFAD has Key Blob Processing */
380380
#define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (1)
381381
/* @brief OTFAD has interrupt request enable */
382-
#define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (1)
382+
#define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0)
383383
/* @brief OTFAD has Force Error */
384384
#define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (1)
385385

@@ -462,11 +462,11 @@
462462
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
463463
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
464464
/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
465-
#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0)
465+
#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
466466
/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
467467
#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0)
468468
/* @brief Number of TAMPER. */
469-
#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (1)
469+
#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0)
470470

471471
/* SRC module features */
472472

‎sdk/devices/MIMXRT1011/drivers/driver_flexio_i2s_edma_MIMXRT1011.cmake‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
1111
)
1212

1313

14-
include(driver_edma_MIMXRT1011)
15-
1614
include(driver_flexio_i2s_MIMXRT1011)
1715

16+
include(driver_edma_MIMXRT1011)
17+

‎sdk/devices/MIMXRT1011/drivers/driver_flexio_spi_edma_MIMXRT1011.cmake‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
1111
)
1212

1313

14-
include(driver_edma_MIMXRT1011)
15-
1614
include(driver_flexio_spi_MIMXRT1011)
1715

16+
include(driver_edma_MIMXRT1011)
17+

‎sdk/devices/MIMXRT1011/drivers/fsl_adc_etc.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2016, Freescale Semiconductor, Inc.
3-
* Copyright 2016-2020 NXP
3+
* Copyright 2016-2021 NXP
44
* All rights reserved.
55
*
66
* SPDX-License-Identifier: BSD-3-Clause
@@ -343,19 +343,19 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr
343343
tmp32 |= (uint32_t)kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in
344344
fsl_adc_etc.h file. */
345345
}
346-
if (((base->DONE2_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex)) != 0U)
346+
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex)) != 0U)
347347
{
348348
tmp32 |= (uint32_t)kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in
349349
fsl_adc_etc.h file. */
350350
}
351351
#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
352-
if (((base->DONE2_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex)) != 0U)
352+
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex)) != 0U)
353353
{
354354
tmp32 |= (uint32_t)kADC_ETC_Done3StatusFlagMask; /* Customized DONE3 status flags mask, which is defined in
355355
fsl_adc_etc.h file. */
356356
}
357357
#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
358-
if (((base->DONE2_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex)) != 0U)
358+
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex)) != 0U)
359359
{
360360
tmp32 |= (uint32_t)kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in
361361
fsl_adc_etc.h file. */
@@ -382,17 +382,17 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig
382382
}
383383
if (0U != (mask & (uint32_t)kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
384384
{
385-
base->DONE2_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex);
385+
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex);
386386
}
387387
#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
388388
if (0U != (mask & (uint32_t)kADC_ETC_Done3StatusFlagMask)) /* Write 1 to clear DONE3 status flags. */
389389
{
390-
base->DONE2_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex);
390+
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex);
391391
}
392392
#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
393393
if (0U != (mask & (uint32_t)kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
394394
{
395-
base->DONE2_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex);
395+
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex);
396396
}
397397
}
398398

‎sdk/devices/MIMXRT1011/drivers/fsl_adc_etc.h‎

Lines changed: 1 addition & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -20,26 +20,10 @@
2020
* Definitions
2121
******************************************************************************/
2222
/*! @brief ADC_ETC driver version */
23-
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0. */
23+
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
2424
/*! @brief The mask of status flags cleared by writing 1. */
2525
#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
2626

27-
#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
28-
#if defined(ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
29-
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK
30-
#define DONE2_ERR_IRQ DONE2_3_ERR_IRQ
31-
#endif /* ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK */
32-
33-
#if defined(ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
34-
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK
35-
#endif /* ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK */
36-
37-
#if defined(ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
38-
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK
39-
#endif /* ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK */
40-
41-
#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
42-
4327
/*!
4428
* @brief ADC_ETC customized status flags mask.
4529
*/

‎sdk/devices/MIMXRT1011/drivers/fsl_clock.c‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,20 +1076,16 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
10761076
*/
10771077
void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider)
10781078
{
1079-
uint32_t tmp32;
1080-
1081-
tmp32 = CCM->CCOSR;
10821079
if (selection == kCLOCK_DisableClockOutput1)
10831080
{
1084-
tmp32 &= ~CCM_CCOSR_CLKO1_EN_MASK;
1081+
CCM->CCOSR &= ~(CCM_CCOSR_CLKO1_EN_MASK | CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK);
10851082
}
10861083
else
10871084
{
1088-
tmp32 |= CCM_CCOSR_CLKO1_EN_MASK;
1089-
tmp32 &= ~(CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK);
1090-
tmp32 |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider);
1085+
CCM->CCOSR &= ~(CCM_CCOSR_CLKO1_EN_MASK | CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK);
1086+
CCM->CCOSR |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider);
1087+
CCM->CCOSR |= CCM_CCOSR_CLKO1_EN_MASK;
10911088
}
1092-
CCM->CCOSR = tmp32;
10931089
}
10941090

10951091
/*!

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