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update rt1064 sdk to version 2.8.5
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‎sdk/devices/MIMXRT1064/MIMXRT1064.h‎

Lines changed: 2298 additions & 53 deletions
Large diffs are not rendered by default.

‎sdk/devices/MIMXRT1064/MIMXRT1064.xml‎

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30251,6 +30251,78 @@ SPDX-License-Identifier: BSD-3-Clause
3025130251
</field>
3025230252
</fields>
3025330253
</register>
30254+
<register>
30255+
<name>USB1_LOOPBACK</name>
30256+
<description>USB Loopback Test Register</description>
30257+
<addressOffset>0x1E0</addressOffset>
30258+
<size>32</size>
30259+
<access>read-write</access>
30260+
<resetValue>0</resetValue>
30261+
<resetMask>0xFFFFFFFF</resetMask>
30262+
<fields>
30263+
<field>
30264+
<name>UTMI_TESTSTART</name>
30265+
<description>Setting this bit can enable 1</description>
30266+
<bitOffset>0</bitOffset>
30267+
<bitWidth>1</bitWidth>
30268+
<access>read-write</access>
30269+
</field>
30270+
</fields>
30271+
</register>
30272+
<register>
30273+
<name>USB1_LOOPBACK_SET</name>
30274+
<description>USB Loopback Test Register</description>
30275+
<addressOffset>0x1E4</addressOffset>
30276+
<size>32</size>
30277+
<access>read-write</access>
30278+
<resetValue>0</resetValue>
30279+
<resetMask>0xFFFFFFFF</resetMask>
30280+
<fields>
30281+
<field>
30282+
<name>UTMI_TESTSTART</name>
30283+
<description>Setting this bit can enable 1</description>
30284+
<bitOffset>0</bitOffset>
30285+
<bitWidth>1</bitWidth>
30286+
<access>read-write</access>
30287+
</field>
30288+
</fields>
30289+
</register>
30290+
<register>
30291+
<name>USB1_LOOPBACK_CLR</name>
30292+
<description>USB Loopback Test Register</description>
30293+
<addressOffset>0x1E8</addressOffset>
30294+
<size>32</size>
30295+
<access>read-write</access>
30296+
<resetValue>0</resetValue>
30297+
<resetMask>0xFFFFFFFF</resetMask>
30298+
<fields>
30299+
<field>
30300+
<name>UTMI_TESTSTART</name>
30301+
<description>Setting this bit can enable 1</description>
30302+
<bitOffset>0</bitOffset>
30303+
<bitWidth>1</bitWidth>
30304+
<access>read-write</access>
30305+
</field>
30306+
</fields>
30307+
</register>
30308+
<register>
30309+
<name>USB1_LOOPBACK_TOG</name>
30310+
<description>USB Loopback Test Register</description>
30311+
<addressOffset>0x1EC</addressOffset>
30312+
<size>32</size>
30313+
<access>read-write</access>
30314+
<resetValue>0</resetValue>
30315+
<resetMask>0xFFFFFFFF</resetMask>
30316+
<fields>
30317+
<field>
30318+
<name>UTMI_TESTSTART</name>
30319+
<description>Setting this bit can enable 1</description>
30320+
<bitOffset>0</bitOffset>
30321+
<bitWidth>1</bitWidth>
30322+
<access>read-write</access>
30323+
</field>
30324+
</fields>
30325+
</register>
3025430326
<register>
3025530327
<name>USB1_MISC</name>
3025630328
<description>USB Misc Register</description>
@@ -31077,6 +31149,78 @@ SPDX-License-Identifier: BSD-3-Clause
3107731149
</field>
3107831150
</fields>
3107931151
</register>
31152+
<register>
31153+
<name>USB2_LOOPBACK</name>
31154+
<description>USB Loopback Test Register</description>
31155+
<addressOffset>0x240</addressOffset>
31156+
<size>32</size>
31157+
<access>read-write</access>
31158+
<resetValue>0</resetValue>
31159+
<resetMask>0xFFFFFFFF</resetMask>
31160+
<fields>
31161+
<field>
31162+
<name>UTMI_TESTSTART</name>
31163+
<description>Setting this bit can enable 1</description>
31164+
<bitOffset>0</bitOffset>
31165+
<bitWidth>1</bitWidth>
31166+
<access>read-write</access>
31167+
</field>
31168+
</fields>
31169+
</register>
31170+
<register>
31171+
<name>USB2_LOOPBACK_SET</name>
31172+
<description>USB Loopback Test Register</description>
31173+
<addressOffset>0x244</addressOffset>
31174+
<size>32</size>
31175+
<access>read-write</access>
31176+
<resetValue>0</resetValue>
31177+
<resetMask>0xFFFFFFFF</resetMask>
31178+
<fields>
31179+
<field>
31180+
<name>UTMI_TESTSTART</name>
31181+
<description>Setting this bit can enable 1</description>
31182+
<bitOffset>0</bitOffset>
31183+
<bitWidth>1</bitWidth>
31184+
<access>read-write</access>
31185+
</field>
31186+
</fields>
31187+
</register>
31188+
<register>
31189+
<name>USB2_LOOPBACK_CLR</name>
31190+
<description>USB Loopback Test Register</description>
31191+
<addressOffset>0x248</addressOffset>
31192+
<size>32</size>
31193+
<access>read-write</access>
31194+
<resetValue>0</resetValue>
31195+
<resetMask>0xFFFFFFFF</resetMask>
31196+
<fields>
31197+
<field>
31198+
<name>UTMI_TESTSTART</name>
31199+
<description>Setting this bit can enable 1</description>
31200+
<bitOffset>0</bitOffset>
31201+
<bitWidth>1</bitWidth>
31202+
<access>read-write</access>
31203+
</field>
31204+
</fields>
31205+
</register>
31206+
<register>
31207+
<name>USB2_LOOPBACK_TOG</name>
31208+
<description>USB Loopback Test Register</description>
31209+
<addressOffset>0x24C</addressOffset>
31210+
<size>32</size>
31211+
<access>read-write</access>
31212+
<resetValue>0</resetValue>
31213+
<resetMask>0xFFFFFFFF</resetMask>
31214+
<fields>
31215+
<field>
31216+
<name>UTMI_TESTSTART</name>
31217+
<description>Setting this bit can enable 1</description>
31218+
<bitOffset>0</bitOffset>
31219+
<bitWidth>1</bitWidth>
31220+
<access>read-write</access>
31221+
</field>
31222+
</fields>
31223+
</register>
3108031224
<register>
3108131225
<name>USB2_MISC</name>
3108231226
<description>USB Misc Register</description>

‎sdk/devices/MIMXRT1064/MIMXRT1064_features.h‎

Lines changed: 71 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.0, 2018-11-16
4-
** Build: b190319
4+
** Build: b200211
55
**
66
** Abstract:
77
** Chip specific module features.
88
**
99
** Copyright 2016 Freescale Semiconductor, Inc.
10-
** Copyright 2016-2019 NXP
10+
** Copyright 2016-2020 NXP
1111
** All rights reserved.
1212
**
1313
** SPDX-License-Identifier: BSD-3-Clause
@@ -123,6 +123,8 @@
123123
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
124124
/* @brief USBPHY availability on the SoC. */
125125
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
126+
/* @brief USB_ANALOG availability on the SoC. */
127+
#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1)
126128
/* @brief USDHC availability on the SoC. */
127129
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
128130
/* @brief WDOG availability on the SoC. */
@@ -147,6 +149,8 @@
147149

148150
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
149151
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
152+
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
153+
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (0)
150154

151155
/* AOI module features */
152156

@@ -207,6 +211,11 @@
207211
/* @brief Has extra MB interrupt or common one. */
208212
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
209213

214+
/* CCM module features */
215+
216+
/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
217+
#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (1)
218+
210219
/* CMP module features */
211220

212221
/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
@@ -222,6 +231,23 @@
222231
/* @brief Has DAC Test function in CMP (register DACTEST). */
223232
#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
224233

234+
/* DCDC module features */
235+
236+
/* @brief Has CTRL register (register CTRL0/1). */
237+
#define FSL_FEATURE_DCDC_HAS_CTRL_REG (0)
238+
/* @brief DCDC VDD output count. */
239+
#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1)
240+
/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */
241+
#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0)
242+
/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */
243+
#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0)
244+
/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */
245+
#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0)
246+
/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */
247+
#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0)
248+
/* @brief Has register bit field REG3[REG_FBK_SEL]). */
249+
#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0)
250+
225251
/* EDMA module features */
226252

227253
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
@@ -266,6 +292,18 @@
266292
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
267293
/* @brief Has Additional 1588 Timer Channel Interrupt. */
268294
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
295+
/* @brief Support Interrupt Coalesce for each instance */
296+
#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1)
297+
/* @brief Queue Size for each instance. */
298+
#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1)
299+
/* @brief Has AVB Support for each instance. */
300+
#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0)
301+
/* @brief Has Timer Pulse Width control for each instance. */
302+
#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1)
303+
/* @brief Has Extend MDIO Support for each instance. */
304+
#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
305+
/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
306+
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0)
269307

270308
/* EWM module features */
271309

@@ -305,13 +343,19 @@
305343
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
306344
/* @brief Total Bank numbers */
307345
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
346+
/* @brief Has FLEXRAM_MAGIC_ADDR. */
347+
#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (0)
308348

309349
/* FLEXSPI module features */
310350

311351
/* @brief FlexSPI AHB buffer count */
312352
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
313353
/* @brief FlexSPI has no data learn. */
314354
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
355+
/* @brief There is AHBBUSERROREN bit in INTEN register. */
356+
#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0)
357+
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
358+
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
315359

316360
/* GPC module features */
317361

@@ -442,7 +486,12 @@
442486

443487
/* OCOTP module features */
444488

445-
/* No feature definitions */
489+
/* @brief Has timing control, (register TIMING). */
490+
#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1)
491+
/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
492+
#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0)
493+
/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
494+
#define FSL_FEATURE_OCOTP_HAS_STATUS (0)
446495

447496
/* PIT module features */
448497

@@ -464,24 +513,12 @@
464513

465514
/* PWM module features */
466515

467-
/* @brief Number of each EflexPWM module channels (outputs). */
468-
#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
469-
/* @brief Number of EflexPWM module A channels (outputs). */
470-
#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
471-
/* @brief Number of EflexPWM module B channels (outputs). */
472-
#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
473-
/* @brief Number of EflexPWM module X channels (outputs). */
474-
#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
475-
/* @brief Number of each EflexPWM module compare channels interrupts. */
476-
#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
477-
/* @brief Number of each EflexPWM module reload channels interrupts. */
478-
#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
479-
/* @brief Number of each EflexPWM module capture channels interrupts. */
480-
#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
481-
/* @brief Number of each EflexPWM module reload error channels interrupts. */
482-
#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
483-
/* @brief Number of each EflexPWM module fault channels interrupts. */
484-
#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
516+
/* @brief If EflexPWM has module A channels (outputs). */
517+
#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
518+
/* @brief If EflexPWM has module B channels (outputs). */
519+
#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
520+
/* @brief If EflexPWM has module X channels (outputs). */
521+
#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
485522
/* @brief Number of submodules in each EflexPWM module. */
486523
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
487524

@@ -589,6 +626,8 @@
589626
#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
590627
/* @brief There is WDOG3_RST_B bit in SRSR register. */
591628
#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
629+
/* @brief There is JTAG_SW_RST bit in SRSR register. */
630+
#define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1)
592631
/* @brief There is SW bit in SRSR register. */
593632
#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
594633
/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
@@ -627,6 +666,13 @@
627666
/* @brief Number of endpoints supported */
628667
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
629668

669+
/* USBPHY module features */
670+
671+
/* @brief USBPHY contain DCD analog module */
672+
#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
673+
/* @brief USBPHY has register TRIM_OVERRIDE_EN */
674+
#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0)
675+
630676
/* USDHC module features */
631677

632678
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
@@ -637,6 +683,10 @@
637683
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
638684
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
639685
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
686+
/* @brief USDHC has reset control */
687+
#define FSL_FEATURE_USDHC_HAS_RESET (0)
688+
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
689+
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
640690

641691
/* XBARA module features */
642692

‎sdk/devices/MIMXRT1064/arm/MIMXRT1064_QSPI_4KB_SEC.FLM‎

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